Accepted DATE'26 Paper

📢 We at #TECO are delighted that our work, “Diagnostic Test Generation for Fault Localization in Printed Neuromorphic Circuits,” was presented at #DATE26 in Verona by Alexander Studt and Tara Gheshlaghi.
As #PrintedElectronics and printed neuromorphic circuits (#pNCs) enable cost-effective, flexible, and low-power intelligent edge systems, manufacturing reliability remains a key challenge. Additive fabrication processes can introduce variations and structural defects that significantly affect circuit functionality, making testing and diagnosis essential for reliable and scalable deployment. In this work, we introduce a diagnostic test pattern generation framework for fault localization in printed neuromorphic circuits under black-box access. While traditional automatic test pattern generation focuses on fault detection, our approach explicitly optimizes for fault distinguishability, enabling more precise localization of defective subcircuits.

Key results include:
-      Up to 20.7% higher diagnostic coverage compared to detection-only test generation
-      Up to 3.6× fewer undetectable subcircuits at the same test budget
-      Compact test sets that limit storage overhead while improving diagnostic effectiveness

Our results show that diagnostic-aware test generation can substantially improve fault localization in printed neuromorphic hardware while providing valuable insights for yield improvement and reducing downstream inspection costs. We see this as an important step toward reliable and scalable neuromorphic computing hardware manufactured using additive processes.

You can access the accompanying paper here:
🔗 https://lnkd.in/etasq9E4

#DATE #PrintedElectronics #NeuromorphicComputing #EdgeAI #HardwareTesting #AIHardware #ResearchInnovation #TECO